8-bit CPU's, The Monolith, and The Metropolis

Maker Faire Bay Area 2026

September 25th-27th

The Monolith is a Harvard-architecture CPU built on 24 breadboards. It features a dual-isolated bus system — Bus A and Bus B operate independently but can pass data to each other in either direction. Two fully separate ALUs handle arithmetic in parallel: ALU1 uses registers A & B, ALU2 uses X & Y. Both support full add/subtract with latched operations, meaning the CPU locks in its current mode rather than re-evaluating it every cycle. Flags are heavily filtered based on context — the mode, the operation, and the state of other signals all influence what gets flagged and what gets ignored, preventing false positives. Conditional branching supports JN, JZ, and JC. A 15-bit program counter allows addressing up to 32KB of ROM. Two 256-entry register banks give it massive storage headroom. I/O includes two output latches, one bidirectional buffer, and a dedicated line that can assert HIGH or LOW.

The Metropolis is a leaner Harvard architecture companion CPU. Its dual buses are connected rather than isolated, keeping the design simpler. A single ALU with the same context-aware flag filtering and latched add/subtract handles all arithmetic, while A & B feed it, and X & Y registers communicate freely with both buses. An 8-bit program counter addresses 256 bytes of ROM. Dedicated hardware handles counting and XNOR comparisons, offloading those tasks entirely from the ALU. A CALL/RET system with a hardware Return Register that instantly latches PC+1 enables full subroutine support. I/O is minimal — one output latch and a LOW signal line, typically used to drive an external buffer.